Jingyuan (Wiliam) Li

Jingyuan (Wiliam) Li

李敬元

Analog/Mixed-Signal IC Design

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publications

Pneumonia Image Classification based on Convolutional Neural Network

Published in 2022 IEEE 5th International Conference on Automation, Electronics and Electrical Engineering (AUTEEE), 2022

This paper introduces an improved convolutional neural network (CNN), which is used to classify and recognize different types of pneumonia using chest CT images. This classifying model is built and trained on thousands of real clinical chest CT images, which respectively belong to patients with viral pneumonia, patients with bacterial pneumonia, patients with COVID-19, and nonpatients. To richen the dataset and avoid over-fitting, pre-processing methods are recommended. Then the paper elaborates the structure of the new network and compares the performance of different optimizers in this dataset. Finally, the accuracy, specificity, precision, sensitivity, and F1-score of the model are calculated to quantitatively evaluate the performance of this model. The final training accuracy is about 97.9%, and the test accuracy is 91.8%.

Recommended citation: Y. Yulin, P. Yuhang, D. Jiakai, L. Jingyuan and T. T. Toe, "Pneumonia image classification based on convolutional neural network," 2022 IEEE 5th International Conference on Automation, Electronics and Electrical Engineering (AUTEEE), Shenyang, China, 2022, pp. 316-320, doi: 10.1109/AUTEEE56487.2022.9994305.
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talks

Embedded Password Security System Design

Published:

  • Designed and implemented a microcontroller-based password security system using NUCLEO-L432KC and Mbed OS.
  • Developed the embedded software in C++, utilizing UART communication between the microcontroller and PC for password verification and system feedback.
  • Integrated LED indicators and a seven-segment display to provide real-time visual status of password correctness and system lock state.
  • Implemented system logic allowing three password attempts, after which the system locks and requires manual reset via a push button.
  • Conducted hardware prototyping and functional testing on a breadboard to verify system performance under multiple test scenarios.
  • Achieved successful operation with accurate password validation, lock mechanism, and user feedback, demonstrating strong skills in embedded system design, hardware-software integration, and real-time control logic.

Pneumonia Image Classification based on Convolutional Neural Network

Published:

  • Developed an CNN model aimed at classifying pneumonia pathogens using patients’ chest CT images.
  • Treated 18,000 chest CT scans from patients with COVID-19, SARS, and bacteria infected.
  • Constructed a model of 3 convolutional layers and 3 max-pooling layers.
  • Performed gradient comparison analysis to define the optimal parameter of each layer.
  • Achieved a training accuracy of 97.9% and a testing accuracy of 91.8%.
  • Scored 90 and was awarded “Distinction” in project evaluation (the highest level attainable).

Design and Analysis of a 2.4 GHz Printed Dipole Antenna

Published:

  • Led a team of three to design a 2.4 GHz antenna suitable for Bluetooth application.
  • Constructed the antenna by employing a half-wave printed dipole model and simulated the design’s performance and efficiency using HFSS software.
  • Utilized a 0.787 mm-thick PCB board made of Rogers 5880, determined the practical arm length to 54.25 mm using parameter sweeping, and verified its function by 3D gain plot and VSWR analysis.
  • Completed the project successfully and ranked 3rd in the cohort of the EMFT course.

Design of a Multitasking Smart Robot Vehicle

Published:

  • Participated in a team of 10 students to construct a smart robot vehicle capable of performing 6 tasks, including line tracking and pattern recognition.
  • Designed a set of inter-board communication method, helping to replace the function of a complex controlled unit with only a camera module.
  • Constructed the car’s distance measurement system using MbedOS and HC-SR04 ultrasonic sensors and developed an algorithm in Micro Python which could assign a flag for data ignorance to filter out the wrong data generated the distance sensors.
  • Produced a pan-silt camera holder and tent-shaped mechanical arm gripper using SolidWorks modeling and 3D printing.
  • Project Information

Research on the Modeling of Computing-in-Memory Architecture with SRAM-based Macro

Published:

  • Constructed a behavioral model of PT-8T SRAM in-memory-computation cell by Verilog which can perform Boolean AND operation between the data stored in that cell and an extra input.
  • Built the SRAM-CIM in 4 banks, each bank had 64 lines of 8-bit SRAM-CIM cells, aiming at storing and processing grayscale/RGB data.
  • Constructed the peripheral control circuits, including the CIM value decoder and a 7-level adder tree, enabling the CIM array to perform Multiplication & Accumulation operation in convolutional neural networks.
  • Designed an address controller to store a value into several address places each time, which improved the computational parallelism.
  • Evaluated the performance by emulating the computation process of convolutional layer computation through the circuit macro, which confirmed that only 34% of clock periods was required when using 3*3 kernel compared with conventional computation methods.

Design of a 2-Stage Folded Cascode Amplifier in 180nm CMOS

Published:

  • Improved a 2-stage amplifier system consisting of 31 transistors, with folded cascode-common source structure and DC biasing circuits.
  • Calculated the optimal expected gain, MOSFET overdrive voltage, sizes and power consumption based on the Gm/Id relation in PDK library.
  • Designed the DC biasing circuits with a constant-gm reference and current mirror technology.
  • Adopted RC compensation between 2 stages of amplifier for poles splitting to ensure enough phase margin.
  • Achieved a gain of 77 dB, unity gain bandwidth over 30 MHz, and phase margin over 67 degrees, and power consumption under 2.3 milliwatt.

Design of a 3-Stage Telescope Operational Amplifier in TSMC 65nm

Published:

  • Designed an operational amplifier for the transimpedance amplifier in a Bluetooth receiver, achieving a gain greater than 60 dB and a gain-bandwidth product close to 1 GHz, with a 0.5 V common-mode input and output range.
  • Adopted a cascode–common source–source follower structure with PMOS input, and introduced Miller compensation between the first and second stages to meet the requirements for high gain and precise bandwidth. After determining the circuit topology, calculated transistor dimensions, compensation capacitance, and zeroing resistance based on mobility and other relevant data from the 65nm PDK.
  • Designed a common-mode feedback circuit that forms a feedback loop between the output node and the gate bias point of the NMOS current source, to stabilize the common-mode level and improve input-output linearity.
  • Designed a constant-gm reference circuit to generate a stable bias current source, and built the amplifier’s biasing network using current mirrors and replicated bias branches.
  • Achieved a gain of 61.6 dB, a 1 GHz gain-bandwidth product, a phase margin of 73 degrees, and a gain margin of 18 dB.

Design of a Low Power ECG Amplifier in 180nm CMOS

Published:

  • Designed a low power ECG amplifier with instrumentation amplifier (IA) structure, which consisted of a fully differential input buffer, a differential amplifier and a “drive-right-leg” common mode feedback amplifier with referenced input.
  • Constructed a 2-stage amplifier with differential pair-common source structure, which achieves an intrinsic gain of 4000V/V.
  • Adopted PMOS differential pair input and sized them to operate in sub-threshold region for noise reduction.
  • Achieved a differential mode gain of 40dB, CMRR of 85dB in range of 1-250Hz, a total power consumption of 3.8 millionth watts and a total input-referred noise below 3 millionth Vin.

Design of a 10Gb/s Tunable Voltage-Mode Transmitter Driver with 3-Tap FFE in 65nm CMOS

Published:

  • Measured a pulse response on a channel model and calculated the tap weights based on zero-forcing method in MATLAB.
  • Designed a 5-bit voltage-mode transmitter driver with rigorous sizing for impedance matching under DC simulation.
  • Adopted foot transistors and introduced enable signal to realize the function of tunable weights under different data rates.
  • Conducted comparisons with current-mode driver and tested the tunability control using pass gate.

Design of a 9-bit SAR ADC Layout in 65nm CMOS (Taped-Out)

Published:

  • Designed a clock-controlled differential comparator and improved device matching using common-centroid MOSFET layout techniques, achieving compensation voltage resolution below 1 LSB and propagation delay under 600 ps across process corners.
  • Developed a three-layer interdigitated unit metal capacitor with a capacitance of 5 fF by optimizing parasitic parameters; constructed a 9-bit common-centroid symmetrical CDAC array based on this unit; added dummy structures at the CDAC array edges to ensure adjacent bit capacitor mismatch ratio below 0.2%.
  • Implemented the successive approximation algorithm in Verilog and converted it into digital layout for the SAR ADC control logic using automated scripts.
  • Designed a decoupling capacitor using NMOS devices and 7-layer interdigitated metal structures; completed top-level schematic and Pad Ring layout; verified full-chip DRC and LVS compliance.
  • Measured quantization noise and distortion noise of the SAR ADC before and after filling, and for the full chip; achieved a final signal-to-noise ratio (SNR) of approximately 49 dB, qualifying for tape-out.
  • Design a motherboard-daughter PCB system including COB package, power, SE-DE, buffers etc., for the SAR ADC testing.

Design of a 1.8V–0.8V DC-DC Buck Converter Based on 45nm CMOS

Published:

  • Built an ideal buck converter macro-model to verify design feasibility; extracted unit switching transistor parameters using Cadence; calculated energy conversion efficiency with MATLAB to obtain the optimal trade-off between efficiency and power-area figure of merit, thereby determining transistor dimensions and inductor size.
  • Designed an error amplifier with a five-transistor structure achieving 60 dB high gain, and implemented Type-III compensation to enhance feedback network stability.
  • Designed low-dropout regulators (LDOs) with a reference voltage of 1.2V and output voltages of 1V and 0.9V to supply power for switching and digital circuits.
  • Developed a three-level level-shifter covering voltage ranges of 0–0.9V, 0.9–1.8V, and 0–1.8V, compatible with both PMOS and NMOS gate drivers.
  • Designed a ramp signal generator and a PWM signal generator that, in coordination with the feedback loop, generate control signals for the switching circuit to operate at the required frequency and duty cycle for 0.8V output.
  • Simulated and verified the overall closed-loop performance of the buck converter, achieving 85.5% energy conversion efficiency and 8.66 mV output ripple, while maintaining stable operation under input voltages of 1.6V–2.0V and temperature variations from −40℃ to 80℃.

teaching

Artificial Intelligence Summer Research Intern

Summer School, Nanyang Technological University, Business AI Lab, 2022

  • Developed an CNN model aimed at classifying pneumonia pathogens using patients’ chest CT images.
  • Treated 18,000 chest CT scans from patients with COVID-19, SARS, and bacteria infected.
  • Built and optimized a model with 3 convolutional layers.
  • Achieved training accuracy of 97.9% and testing accuracy of 91.8%.
  • Scored 90 and was awarded “Distinction” in project evaluation (the highest level attainable).