Design of a 2-Stage Folded Cascode Amplifier in 180nm CMOS
Date:
- Improved a 2-stage amplifier system consisting of 31 transistors, with folded cascode-common source structure and DC biasing circuits.
- Calculated the optimal expected gain, MOSFET overdrive voltage, sizes and power consumption based on the Gm/Id relation in PDK library.
- Designed the DC biasing circuits with a constant-gm reference and current mirror technology.
- Adopted RC compensation between 2 stages of amplifier for poles splitting to ensure enough phase margin.
- Achieved a gain of 77 dB, unity gain bandwidth over 30 MHz, and phase margin over 67 degrees, and power consumption under 2.3 milliwatt.